In finance, a foreign exchange option (commonly shortened to just FX option or currency option) is a derivative financial instrument that gives the right but not the obligation to exchange money denominated in one currency into another currency at a pre-agreed exchange rate on a specified date.[1] See Foreign exchange derivative. The foreign exchange options market is the deepest, largest and most liquid market for options of any kind. Most trading is over the counter (OTC) and is lightly regulated, but a fraction is traded on exchanges like the International Securities Exchange, Philadelphia Stock Exchange, or the Chicago Mercantile Exchange for options on futures contracts. The global market for exchange-traded currency options was notionally valued by the Bank for International Settlements at $158.3 trillion in 2005 For example, a GBPUSD contract could give the owner the right to sell?1,000,000 and buy $2,000,000 on December 31. In this case the pre-agreed exchange rate, or strike price, is 2.0000 USD per GBP (or GBP/USD 2.00 as it is typically quoted) and the notional amounts (notionals) are?1,000,000 and $2,000,000. This type of contract is both a call on dollars and a put on sterling, and is typically called a GBPUSD put, as it is a put on the exchange rate; although it could equally be called a USDGBP call.

If the rate is lower than 2.0000 on December 31 (say 1.9000), meaning that the dollar is stronger and the pound is weaker, then the option is exercised, allowing the owner to sell GBP at 2.0000 and immediately buy it back in the spot market at 1.9000, making a profit of (2.0000 GBPUSD? 1.9000 GBPUSD)? 1,000,000 GBP = 100,000 USD in the process. If instead they take the profit in GBP (by selling the USD on the spot market) this amounts to 100,000 / 1.9000 = 52,632 GBP. Although FX options are more widely used today than ever before, few multinationals act as if they truly understand when and why these instruments can add to shareholder value. To the contrary, much of the time corporates seem to use FX options to paper over accounting problems, or to disguise the true cost of speculative positioning, or sometimes to solve internal control problems.

The standard clich? About currency options affirms without elaboration their power to provide a company with upside potential while limiting the downside risk. Options are typically portrayed as a form of financial insurance, no less useful than property and casualty insurance.

Intel Quartus Prime Pro Edition Handbook Volume 1 Design and Compilation. Introduction to Intel Quartus Prime Pro Edition. (This introduction is not a part of IEEE Std 1076.3-1997, IEEE Standard VHDL Synthesis Packages.) This standard. Ing vector types for representing signed or unsigned integer values and providing standard interpretations of. That define arithmetic, shift, and type conversion operations on those types.

This glossy rationale masks the reality: if it is insurance then a currency option is akin to buying theft insurance to protect against flood risk. The truth is that the range of truly non-speculative uses for currency options, arising from the normal operations of a company, is quite small.

In reality currency options do provide excellent vehicles for corporates' speculative positioning in the guise of hedging. Corporates would go better if they didn't believe the disguise was real. Let's start with six of the most common myths about the benefits of FX options to the international corporation -- myths that damage shareholder values. Historically, the currency derivative pricing literature and the macroeconomics literature on FX determination have progressed separately. In this Chapter I argue the joint study of these two strands of literature and give an overview of FX option pricing concepts and terminology crucial for this interdisciplinary study. I also explain the three sources of information about market expectations and perception of risk that can be extracted from FX option prices and review empirical methods for extracting option-implied densities of future exchange rates. As an illustration, I conclude the Chapter by investigating time series dynamics of option-implied measures of FX risk vis-a-vis market events and US government policy actions during the period January 2007 to December 2008.

Chapter 2: This Chapter proposes using foreign exchange (FX) options with different strike prices and maturities to capture both FX expectations and risks. We show that exchange rate movements, which are notoriously difficult to model empirically, are well-explained by the term structures of forward premia and options-based measures of FX expectations and risk. Although this finding is to be expected, expectations and risk have been largely ignored in empirical exchange rate modeling. Using daily options data for six major currency pairs, we first show that the cross section options-implied standard deviation, skewness and kurtosis consistently explain not only the conditional mean but also the entire conditional distribution of subsequent currency excess returns for horizons ranging from one week to twelve months.

At June 30 and September 30, the value of the portfolio was?1,050,000. Note, however, that the notional amount of Ridgeway's hedging instrument was only?1,000,000. Therefore, subsequent to the increase in the value of the pound (which is assumed to have occurred on June 30), a portion of Ridgeway's foreign currency exchange risk was not hedged.

For the three-month period ending September 30, exchange rates caused the value of the portfolio to decline by $52,500. Of that amount, only $50,000 was offset by changes in the value of the currency put option. The difference between those amounts ($2,500) represents the exchange rate loss on the unhedged portion of the portfolio (i.e., the 'additional'?50,000 of fair value that arose through increased share prices after entering into the currency hedge). At June 30, the additional?50,000 of stock value had a U.S. Dollar fair value of $45,000. At September 30, using the spot rate of 0.85:1, the fair value of this additional portion of the portfolio declined to $42,500.

Ridge way will exclude from its assessment of hedge effectiveness the portion of the fair value of the put option attributable to time value. That is, Ridgeway will recognize changes in that portion of the put option's fair value in earnings but will not consider those changes to represent ineffectiveness. Aitan Goelman, the CFTC’s Director of Enforcement, stated: “The setting of a benchmark rate is not simply another opportunity for banks to earn a profit.

Countless individuals and companies around the world rely on these rates to settle financial contracts, and this reliance is premised on faith in the fundamental integrity of these benchmarks. The market only works if people have confidence that the process of setting these benchmarks is fair, not corrupted by manipulation by some of the biggest banks in the world.” The Commission finalized rules to implement the Dodd-Frank Wall Street Reform and Consumer Protection Act regarding Regulation of Off-Exchange Retail Foreign Exchange Transactions and Intermediaries. The Commission also finalized Conforming Changes to existing Retail Foreign Exchange Regulations in response to the Dodd-Frank Act. Additional information regarding these final rules is provided below, including rules, factsheets, and details of meetings held between CFTC Staff and outside parties.

The Intel ® Quartus ® Prime software provides a complete design environment for FPGA and SoC designs. The user interface supports easy design entry, fast processing, and straightforward device programming. The Intel ® Quartus ® Prime Pro Edition software enables next generation synthesis, physical optimization, design methodologies, and FPGA architectures. The Intel ® Quartus ® Prime Pro Edition software provides unique features not available in other Intel ® Quartus ® Prime software editions. The Intel ® Quartus ® Prime Pro Edition Compiler is optimized for the latest Intel ® Arria ® 10, Intel ® Cyclone ® 10, and Intel ® Stratix ® 10 devices. The Compiler provides powerful and customizable design processing to achieve the best possible design implementation in silicon.

The Intel ® Quartus ® Prime software makes it easy for you to focus on your design—not on the design tool. The Intel ® Quartus ® Prime Pro Edition software provides unique features not available in other Quartus software products. The modular Compiler streamlines the FPGA development process, and ensures the highest performance for the least effort. The Intel ® Quartus ® Prime Pro Edition software provides the following unique features: • Hyper-Aware Design Flow—use Hyper-Retiming and Fast Forward compilation for the highest performance in Intel ® Stratix ® 10 devices. • Intel ® Quartus ® Prime Pro Edition synthesis—integrates new, stricter language parser supporting all major IEEE RTL languages, with enhanced algorithms, and parallel synthesis capabilities.

Added support for SystemVerilog 2009. • Hierarchical project structure—preserves individual post-synthesis, post-placement, and post-place and route results for each design entity. Allows optimization without impacting other partition placement or routing. • Incremental Fitter Optimizations—run and optimize Fitter stages incrementally.

Each Fitter stage generates detailed reports. • Faster, more accurate I/O placement—plan interface I/O in Interface Planner.

• Platform Designer—builds on the system design and custom IP integration capabilities of Platform Designer. Platform Designer in Intel ® Quartus ® Prime Pro Edition introduces hierarchical isolation between system interconnect and IP components.

• Partial Reconfiguration—support reconfiguration of a portion of the Intel ® Arria ® 10 FPGA, while the remaining FPGA continues to function. • Supports block-based design flows, allowing you to preserve and reuse design blocks at various stages of compilation. Selecting a Quartus Prime Edition Consider the requirements and timeline of your project in determining whether the Intel ® Quartus ® Prime Standard Edition or Intel ® Quartus ® Prime Pro Edition software is most appropriate for you. Use the following factors to inform your decision: • The Intel ® Quartus ® Prime Pro Edition software supports only Intel ® Arria ® 10, Intel ® Cyclone ® 10 GX, and Intel ® Stratix ® 10 devices. If your design targets any other Intel FPGA device, select the Intel ® Quartus ® Prime Standard Edition. • Select the Intel ® Quartus ® Prime Pro Edition if you are beginning a new Intel ® Arria ® 10, Intel ® Cyclone ® 10 GX, or Intel ® Stratix ® 10 design, or if your design requires any unique Intel ® Quartus ® Prime Pro Edition features. • Intel ® Quartus ® Prime Pro Edition software does not support the following Intel ® Quartus ® Prime Standard Edition features: • I/O Timing Analysis • NativeLink third party tool integration • Video and Image Processing Suite IP Cores • Talkback features • Various register merging and duplication settings • Saving a node-level netlist as.vqm • Compare project revisions.

Note: The migration steps for Quartus Prime Lite Edition, Intel ® Quartus ® Prime Standard Edition, and the Quartus II software are identical. For brevity, this section refers to these design tools collectively as 'other Quartus software products.' Migrating to Intel ® Quartus ® Prime Pro Edition requires the following changes to other Quartus software product projects: • Upgrade project assignments and constraints with equivalent Intel ® Quartus ® Prime Pro Edition assignments. • Upgrade all Intel ® FPGA IP core variations and Platform Designer systems in your project.

• Upgrade design RTL to standards-compliant VHDL, Verilog HDL, or SystemVerilog. This document describes each migration step in detail. Intel ® Quartus ® Prime Pro Edition software introduces changes to handling of project assignments and constraints that the Quartus Settings File (.qsf) stores. Upgrade other Quartus software product project assignments and constraints for migration to the Intel ® Quartus ® Prime Pro Edition software. Upgrade other Quartus software product assignments with Assignments >Assignment Editor, by editing the.qsf file directly, or by using a Tcl script. The following sections detail each type project assignment upgrade that migration requires. While the current version of the Intel ® Quartus ® Prime Pro Edition software still accepts entity names in the.qsf, the Compiler ignores the entity name.

The Compiler generates a warning message upon detection of an entity names in the.qsf. Whenever possible, you should remove entity names from assignments, and discontinue reliance on entity-based assignments. Future versions of the Intel ® Quartus ® Prime Pro Edition software may eliminate all support for entity-based assignments. Resolve Timing Constraint Entity Names. Intel ® Quartus ® Prime synthesis generates and automatically names internal design nodes during processing. The Intel ® Quartus ® Prime Pro Edition uses different conventions than other Quartus software products to generate node names during synthesis.

When you synthesize your other Quartus software product project in Intel ® Quartus ® Prime Pro Edition, the synthesis-generated node names may change. If any scripts or constraints depend on the synthesis-generated node names, update the scripts or constraints to match the Intel ® Quartus ® Prime Pro Edition synthesis node names. Region Constraints Per Edition Constraint Type Logic Lock (Standard) Region Support Other Quartus Software Products Logic Lock Region Support Intel ® Quartus ® Prime Pro Edition Fixed rectangular, nonrectangular or non-contiguous regions Full support. Full support. Chip Planner entry Full support.

Full support. Periphery element assignments Supported in some instances. Full support. Use “core-only” regions to exclude the periphery.

Nested (“hierarchical”) regions Supported but separate hierarchy from the user instance tree. Supported in same hierarchy as user instance tree. Reserved regions Limited support for nested or nonrectangular reserved regions.

Reserved regions typically cannot cross I/O columns; use non-contiguous regions instead. Full support for nested and nonrectangular regions. Reserved regions can cross I/O columns without affecting periphery logic if the regions are 'core-only'. Routing regions Limited support via “routing expansion.” No support with hierarchical regions. Full support (including future support for hierarchical regions). Floating or autosized regions Full support.

Region names Regions have names. Regions are identified by the instance name of the constrained logic.

Multiple instances in the same region Full support. Support for non-reserved regions. Create one region per instance, and then specify the same definition for multiple instances to assign to the same area. Not supported for reserved regions.

Member exclusion Full support. No support for arbitrary logic. Use a core-only region to exclude periphery elements. Use non-rectangular regions to include more RAM or DSP columns as needed. Assign Subordinate Logic Lock Instances By default, the Intel ® Quartus ® Prime software constrains every child instance to the Logic Lock region of its parent. Any constraint to a child instance intersects with the constraint of its ancestors. For example, in the following example, all logic beneath “ a b c d” constrains to box (10,10), (15,15), and not (0,0), (15,15).

This result occurs because the child constraint intersects with the parent constraint. Set_instance_assignment –name PLACE_REGION –to a b c 'X10 Y10 X20 Y20'set_instance_assignment –name PLACE_REGION –to a b c d 'X0 Y0 X15 Y15'. Assigned Reserved Logic Lock Regions Optionally reserve an entire Logic Lock region for one instance and any of its subordinate instances. Set_instance_assignment –name PLACE_REGION –to a b c 'X10 Y10 X20 Y20'set_instance_assignment –name RESERVE_PLACE_REGION –to a b c ON# The following assignment causes an error. The logic in e f g is not# legally placeable anywhere:# set_instance_assignment –name PLACE_REGION –to e f g 'X10 Y10 X20 Y20'# The following assignment does *not* cause an error, but is effectively# constrained to the box (20,10), (30,20), since the (10,10),(20,20) box is reserved# for a b cset_instance_assignment –name PLACE_REGION –to e f g 'X10 Y10 X30 Y20' Modify Signal Tap Logic Analyzer Files. If you migrate a project that includes.stp files generated by other Quartus software products, you must make the following changes to migrate to the Intel ® Quartus ® Prime Pro Edition: • Remove entity names from.stp files. The Signal Tap Logic Analyzer allows without error, but ignores, entity names in.stp files.

Remove entity names from.stp files for migration to Intel ® Quartus ® Prime Pro Edition: • Click View >Node Finder to locate and remove appropriate nodes. Use Node Finder options to filter on nodes.

• Click Processing >Start >Start Analysis & Elaboration to repopulate the database and add valid node names. • Remove post-fit nodes. Intel ® Quartus ® Prime Pro Edition uses a different post-fit node naming scheme than other Quartus software products. • Remove post-fit tap node names originating from other Quartus software products. • Click View >Node Finder to locate and remove post-fit nodes.

Use Node Finder options to filter on nodes. • Click Processing >Start Compilation to repopulate the database and add valid post-fit nodes. • Run an initial compilation in Intel ® Quartus ® Prime Pro Edition from the GUI. The Compiler automatically removes Signal Tap assignments originating other Quartus software products. Alternatively, from the command-line, run quartus_stp once on the project to remove outmoded assignments. • Incremental Compilation (partitions)—The current version of the Intel ® Quartus ® Prime Pro Edition software does not support Intel ® Quartus ® Prime Standard Edition incremental compilation.

Remove all incremental compilation feature assignments from other Quartus software product.qsf files before migration. • Intel ® Quartus ® Prime Standard Edition Physical synthesis assignments.

Intel ® Quartus ® Prime Pro Edition software does not support Intel ® Quartus ® Prime Standard Edition Physical synthesis assignments. Remove any of the following assignments from the.qsf file or design RTL (instance assignments) before migration. PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA PHYSICAL_SYNTHESIS_COMBO_LOGIC PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION PHYSICAL_SYNTHESIS_REGISTER_RETIMING PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Upgrade IP Cores and Platform Designer Systems. Upgrade all IP cores and Platform Designer systems in your project for migration to the Intel ® Quartus ® Prime Pro Edition software. The Intel ® Quartus ® Prime Pro Edition software uses standards-compliant methodology for instantiation and generation of IP cores and Platform Designer systems.

Most Intel FPGA IP cores and Platform Designer systems upgrade automatically in the Upgrade IP Components dialog box. Other Quartus software products use a proprietary Verilog configuration scheme within the top level of IP cores and Platform Designer systems for synthesis files. The Intel ® Quartus ® Prime Pro Edition does not support this scheme. To upgrade all IP cores and Platform Designer systems in your project, click Project >Upgrade IP Components. IP Core and Platform Designer System Differences Other Quartus Software Products Intel ® Quartus ® Prime Pro Edition IP and Platform Designer system generation use a proprietary Verilog HDL configuration scheme within the top level of IP cores and Platform Designer systems for synthesis files. This proprietary Verilog HDL configuration scheme prevents RTL entities from ambiguous instantiation errors during synthesis. However, these errors may manifest in simulation.

Resolving this issue requires writing a Verilog HDL configuration to disambiguate the instantiation, delete the duplicate entity from the project, or rename one of the conflicting entities. Intel ® Quartus ® Prime Pro Edition IP strategy resolves these issues. IP and Platform Designer system generation does not use proprietary Verilog HDL configurations.

The compilation library scheme changes in the following ways: • Compiles all variants of an IP core into the same compilation library across the entire project. Intel ® Quartus ® Prime Pro Edition identically names IP cores with identical functionality and parameterization to avoid ambiguous entity instantiation errors. For example, the files for every Intel ® Arria ® 10 PCI Express ® IP core variant compile into the altera_pcie_a10_hip_151 compilation library.

• Simulation and synthesis file sets for IP cores and systems instantiate entities in the same manner. • The generated RTL directory structure now matches the compilation library structure. The Intel ® Quartus ® Prime Pro Edition software introduces a new synthesis engine ( quartus_syn executable).

The quartus_syn synthesis enforces stricter industry-standard HDL structures and supports the following enhancements in this release: • More robust support for SystemVerilog • Improved support for VHDL2008 • New RAM inference engine infers RAMs from GENERATE statements or array of integers • Stricter syntax/semantics check for improved compatibility with other EDA tools Account for these synthesis differences in existing RTL code by ensuring that your design uses standards-compliant VHDL, Verilog HDL, or SystemVerilog. The Compiler generates errors when processing non-compliant RTL. Use the guidelines in this section to modify existing RTL for compatibility with the Intel ® Quartus ® Prime Pro Edition synthesis. Intel ® Quartus ® Prime Pro Edition synthesis uses a different method to define the compilation unit. The Verilog LRM defines the concept of compilation unit as “a collection of one or more Verilog source files compiled together” forming the compilation-unit scope. Items visible only in the compilation-unit scope include macros, global declarations, and default net types.

The contents of included files become part of the compilation unit of the parent file. Modules, primitives, programs, interfaces, and packages are visible in all compilation units. Ensure that your RTL accommodates these changes. Verilog Compilation Unit Differences Other Quartus Software Products Intel ® Quartus ® Prime Pro Edition Synthesis in other Quartus software products follows the Multi-file compilation unit (MFCU) method to select compilation unit files. In MFCU, all files compile in the same compilation unit. Global definitions and directives are visible in all files.

However, the default net type is reset at the start of each file. Intel ® Quartus ® Prime Pro Edition synthesis follows the Single-file compilation unit (SFCU) method to select compilation unit files. In SFCU, each file is a compilation unit, file order is irrelevant, and the macro is only defined until the end of the file.

Verilog HDL Configuration Instantiation Other Quartus Software Products Intel ® Quartus ® Prime Pro Edition From the Example RTL, synthesis automatically finds the mid_config Verilog HDL configuration relating to the instantiated module. From the Example RTL, synthesis does not find the mid_config Verilog HDL configuration. You must instantiate the Verilog HDL configuration directly.

Example RTL: config mid_config;design good_lib.mid;instance mid.sub_inst use good_lib.sub;endconfigmodule test (input a1, output b);mid_config mid_inst (.a1(a1),.b(b)); // in other Quartus products preceding line would have been: //mid mid_inst (.a1(a1),.b(b));endmodulemodule mid (input a1, output b);sub sub_inst (.a1(a1),.b(b));endmodule Update Entity Auto-Discovery. Entity Auto-Discovery Differences Other Quartus Software Products Intel ® Quartus ® Prime Pro Edition Always automatically searches your project directory and search path for undefined entities. Always automatically searches your project directory and search path for undefined entities.

Intel ® Quartus ® Prime Pro Edition synthesis performs auto-discovery earlier in the flow than other Quartus software products. This results in discovery of more syntax errors.

Optionally disable auto-discovery with the following.qsf assignment: set_global_assignment -name AUTO_DISCOVER_AND_SORT OFF Ensure Distinct VHDL Namespace for Each Library. VHDL Namespace Differences Other Quartus Software Products Intel ® Quartus ® Prime Pro Edition For the Example RTL, the analyzer searches all libraries in an unspecified order until the analyzer finds package utilities_pack and uses items from that package. If another library, for example projectLib also contains utilities_pack, the analyzer may use this library instead of myLib.utilites_pack if found before the analyzer searches myLib. For the Example RTL, the analyzer uses the specific utilities_pack in myLib. If utilities_pack does not exist in library myLib, the analyzer generates an error. Example RTL: library myLib; usemyLib.utilities_pack.all; Remove Unsupported Parameter Passing.

SystemVerilog Feature Differences Other Quartus Software Products Intel ® Quartus ® Prime Pro Edition From the Example RTL, synthesis overwrites the value of parameter SIZE in the instance of my_ram instantiated from entity mid-level. From the Example RTL, synthesis generates a syntax error for detection of parameter passing assignments in the.qsf. Specify parameters in the RTL.

The following example shows the supported top-level parameter passing format. This example applies only to the top-level and sets a value of 4 to parameter N: set_parameter -name N 4 Example RTL: set_parameter –entity mid_level –to my_ram –name SIZE 16 Remove Unsized Constant from WYSIWYG Instantiation. Object Declaration Differences Other Quartus Software Products Intel ® Quartus ® Prime Pro Edition From the Example RTL, synthesis initializes the output p_prog_io1 with the value of p_progio1_reg, even though the register declaration occurs in Line 2. From the Example RTL, synthesis generates a syntax error when you specify initial values before declaring the register. Example RTL: 1 output p_prog_io1 = p_prog_io1_reg; 2 reg p_prog_io1_reg; Confine SystemVerilog Features to SystemVerilog Files. SystemVerilog Feature Differences Other Quartus Software Products Intel ® Quartus ® Prime Pro Edition From the Example RTL, synthesis interprets $clog2 in a.v file, even though the Verilog LRM does not define the $clog2 feature.

Other Quartus software products allow other SystemVerilog features in.v files. From the Example RTL, synthesis generates a syntax error for detection of any non-Verilog HDL construct in.v files.

Intel ® Quartus ® Prime Pro Edition synthesis honors SystemVerilog features only in.sv files. Example RTL: localparam num_mem_locations = 1050;wire mem_addr [$clog2(num_mem_locations)-1: 0]; Avoid Assignment Mixing in Always Blocks.

Document Revision History Date Version Changes 2017.11.06 17.1.0 • Described Intel ® Quartus ® Prime tool name updates for Platform Designer (Qsys), Interface Planner (BluePrint), Timing Analyzer (TimeQuest), Eye Viewer (EyeQ), and Advanced Link Analyzer (Advanced Link Analyzer). • Added Verilog HDL Macro example. • Updated for latest Intel ® branding conventions. 2017.05.08 17.0.0 • Removed statement about limitations for safe state machines. The Compiler supports safe state machines.

State machine inference is enabled by default. • Added reference to Block-Based Design Flows. • Removed procedure on manaul dynamic synthesis report generation. The Compiler automatically generates dynamic synthesis reports when enabled. 2016.10.31 16.1.0 • Implemented Intel rebranding. • Added reference to Partial Reconfiguration support. • Added to list of Intel ® Quartus ® Prime Standard Editionfeatures unsupported by Intel ® Quartus ® Prime Pro Edition.

• Added topic on Safe State Machine encoding. • Described unsupported Intel ® Quartus ® Prime Standard Edition physical synthesis options. • Removed deprecated Per-Stage Compilation (Beta) Compilation Flow. • Changed title from 'Remove Filling Vectors' to 'Remove Unsized Constant'. 2016.05.03 16.0.0 • Removed software beta status and revised feature set. • Added topic on Safe State Machine encoding.

• Added Generating Dynamic Synthesis Reports. • Corrected statement about Verilog Compilation Unit. • Corrected typo in Modify Entity Name Assignments. • Added description of Fitter Plan, Place and Route stages, reporting, and optimization.

• Added Per-Stage Compilation (Beta) Compilation Flow. • Added Platform Designer information. • Added OpenCL and Signal Tap with routing preservation as unique Pro Edition features. • Clarified limitations for multiple Logic Lock instances in the same region. Free Cashier Check Printing Software here. 2015.11.02 15.1.0 • First version of document. View basic information about your project in the Project Navigator, Compilation Dashboard, Report panel, and Messages window.

View project elements in the Project Navigator ( View >Project Navigator). The Project Navigator displays key project information, such as design files, IP components, and your project hierarchy. Use the Project Navigator to locate and perform actions of the elements of your project. To access the tabs of the Project Navigator, click the toggle control at the top of the Project Navigator window. Project Navigator Tabs Project Navigator Tab Description Files Lists all design files in the current project.

Right-click design files in this tab to run these commands: • Open the file • Remove the file from project • View file Properties Hierarchy Provides a visual representation of the project hierarchy, specific resource usage information, and device and device family information. Right-click items in the hierarchy to Locate, Set as Top-Level Entity, or define Logic Lock regions or design partitions. Design Units Displays the design units in the project.

Right-click a design unit to Locate in Design File. IP Components Displays the design files that make up the IP instantiated in the project, including Intel ® FPGA IP, Platform Designer components, and third-party IP. Click Launch IP Upgrade Tool from this tab to upgrade outdated IP components. Right-click any IP component to Edit in Parameter Editor.

Setting and Project File Best Practices • Be very careful if you edit any Intel ® Quartus ® Prime data files, such as the Intel ® Quartus ® Prime Project File (.qpf), Intel ® Quartus ® Prime Settings File (.qsf), Quartus IP File (.qip), or Platform Designer System File (.qsys). Typos in these files can cause software errors. For example, the software may ignore settings and assignments. Every Intel ® Quartus ® Prime project revision automatically includes a supporting.qpf that preserves various project settings and constraints that you enter in the GUI or add with Tcl commands.

This file contains basic information about the current software version, date, and project-wide and entity level settings. Due to dependencies between the.qpf and.qsf, avoid manually editing.qsf files. • Do not compile multiple projects into the same directory. Instead, use a separate directory for each project.

• By default, the Intel ® Quartus ® Prime software saves all project output files, such as Text-Format Report Files (.rpt), in the project directory. Instead of manually moving project output files, change your project compilation settings to save them in a separate directory. To save these files into a different directory choose Assignments >Settings >Compilation Process Settings. Turn on Save project output files in specified directory and specify a directory for the output files. Project Archive and Source Control Best Practices Click Project >Archive Project to archive your project for revision control. As you develop your design, your Intel ® Quartus ® Prime project directory contains a variety of source and settings files, compilation database files, output, and report files. You can archive these files using the Archive feature and save the archive for later use or place it under revision control.

• Choose Project >Archive Project >Advanced to open the Advanced Archive Settings dialog box. Trench Warfare Game Mission 4 Burner. • Choose a file set to archive. • Add additional files by clicking Add (optional). To restore your archived project, choose Project >Restore Archived Project.

Restore your project into a new, empty directory. Note: When generating IP cores, do not generate files into a directory that has a space in the directory name or path. Spaces are not legal characters for IP core paths or names. • When you generate an IP core using the IP Catalog, the Intel ® Quartus ® Prime software generates a.qsys (for Platform Designer-generated IP cores) or a.ip file (for Intel ® Quartus ® Prime Pro Edition) or a.qip file.

The Intel ® Quartus ® Prime Pro Edition software automatically adds the generated.ip to your project. In the Intel ® Quartus ® Prime Standard Edition software, add the.qip to your project. Do not add the parameter editor generated file (.v or.vhd) to your design without the.qsys or.qip file.

Otherwise, you cannot use the IP upgrade or IP parameter editor feature. • Plan your directory structure ahead of time. Do not change the relative path between a.qsys file and it's generation output directory. If you must move the.qsys file, ensure that the generation output directory remains with the.qsys file. • Do not add IP core files directly from the /quartus/libraries/megafunctions directory in your project.

Otherwise, you must update the files for each subsequent software release. Instead, use the IP Catalog and then add the.qip to your project. • Do not use IP files that the Intel ® Quartus ® Prime software generates for RAM or FIFO blocks targeting older device families (even though the Intel ® Quartus ® Prime software does not issue an error). The RAM blocks that Intel ® Quartus ® Prime generates for older device families are not optimized for the latest device families. • When generating a ROM function, save the resulting.mif or.hex file in the same folder as the corresponding IP core's.qsys or.qip file. For example, moving all of your project's.mif or.hex files to the same directory causes relative path problems after archiving the design.

• Always use the Intel ® Quartus ® Prime ip-setup-simulation and ip-make-simscript utilities to generate simulation scripts for each IP core or Platform Designer system in your design. These utilities produce a single simulation script that does not require manual update for upgrades to Intel ® Quartus ® Prime software or IP versions.

The New Project Wizard guides you to make intial project settings when you setup a new project. Optimizing project settings helps the Compiler to generate programming files that meet or exceed your specifications. On the Tasks pane, click Settings to access global project settings, including: • Project files list • Synthesis directives and constraints • Logic options and compiler effort levels • Placement constraints • Timing constraint files • Operating temperature limits and conditions • File generation for other EDA tools • Target a device (click Device) • Target a development kit The.qsf stores each project revision’s project settings. The Intel ® Quartus ® Prime Default Settings File ( _assignment_defaults.qdf) stores the default settings and constraints for each new project revision. Optimize project settings to meet your design goals. The Intel ® Quartus ® Prime Design Space Explorer II iteratively compiles your project with various setting combinations to find the optimal setting for your goals.

Alternatively, you can create a project revision or project copy to manually compare various project settings and design combinations. The Intel ® Quartus ® Prime software includes several advisors to help you optimize your design and reduce compilation time.

The advisors listed in the Tools >Advisors menu can provide recommendations based on your project settings and design constraints. You can save multiple, named project revisions within your Intel ® Quartus ® Prime project ( Project >Revisions). Each revision captures a unique set of project settings and constraints, but does not capture any logic design file changes. Use revisions to experiment with different settings while preserving the original. Optimize different revisions for various applications.

Use revisions for the following: • Create a unique revision to optimize a design for different criteria, such as by area in one revision and by f MAX in another revision. • When you create a new revision the default Intel ® Quartus ® Prime settings initially apply. • Create a revision of a revision to experiment with settings and constraints.

The child revision includes all the assignments and settings of the parent revision. You create, delete, and edit revisions in the Revisions dialog box. Each time you create a new project revision, the Intel ® Quartus ® Prime software creates a new.qsf using the revision name. Copying Your Project. The Intel ® Quartus ® Prime software helps you create and manage the logic design files in your project. Logic design files contain the logic that implements your design. When you add a logic design file to the project, the Compiler automatically compiles that file as part of the project.

The Compiler synthesizes your logic design files to generate programming files for your target device. The Intel ® Quartus ® Prime software includes full-featured schematic and text editors, as well as HDL templates to accelerate your design work. The Intel ® Quartus ® Prime software supports VHDL Design Files (.vhd), Verilog HDL Design Files (.v), SystemVerilog (.sv) and schematic Block Design Files (.bdf). In addition, you can combine your logic design files with Intel and third-party IP core design files, including combining components into a Platform Designer system (.qsys). The New Project Wizard prompts you to identify logic design files. Add or remove project files by clicking Project >Add/Remove Files in Project. View the project’s logic design files in the Project Navigator.

Apply appropriate timing constraints to correctly optimize fitting and analyze timing for your design. The Fitter optimizes the placement of logic in the device to meet your specified timing and routing constraints.

Specify timing constraints in the Timing Analyzer ( Tools >Timing Analyzer), or in an.sdc file. Specify constraints for clock characteristics, timing exceptions, and external signal setup and hold times before running analysis. Timing Analyzer reports the detailed information about the performance of your design compared with constraints in the Compilation Report panel. Save the constraints you specify in the GUI in an industry-standard Synopsys Design Constraints File (.sdc). You can subsequently edit the text-based.sdc file directly.

If you refer to multiple.sdc files in a parent.sdc file, the Timing Analyzer reads the.sdc files in the order you list. Introduction to Intel FPGA IP Cores. Intel and strategic IP partners offer a broad portfolio of configurable IP cores optimized for Intel FPGA devices. The Intel ® Quartus ® Prime software installation includes the Intel ® FPGA IP library. Integrate optimized and verified Intel ® FPGA IP cores into your design to shorten design cycles and maximize performance.

The Intel ® Quartus ® Prime software also supports integration of IP cores from other sources. Use the IP Catalog ( Tools >IP Catalog) to efficiently parameterize and generate synthesis and simulation files for your custom IP variation. The Intel ® FPGA IP library includes the following types of IP cores: • Basic functions • DSP functions • Interface protocols • Low power functions • Memory interfaces and controllers • Processors and peripherals This document provides basic information about parameterizing, generating, upgrading, and simulating stand-alone IP cores in the Intel ® Quartus ® Prime software. • Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no project open, select the Device Family in IP Catalog.

• Type in the Search field to locate any full or partial IP core name in IP Catalog. • Right-click an IP core name in IP Catalog to display details about supported devices, to open the IP core's installation folder, and for links to IP documentation. • Click Search for Partner IP to access partner IP information on the web.

The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Intel ® Quartus ® Prime IP file (.ip) for an IP variation in Intel ® Quartus ® Prime Pro Edition projects. • Use the Presets window to apply preset parameter values for specific applications (for select cores).

• Use the Details window to view port and parameter descriptions, and click links to documentation. • Click Generate >Generate Testbench System to generate a testbench system (for select cores). • Click Generate >Generate Example Design to generate an example design (for select cores). • Click Validate System Integrity to validate a system's generic components against companion files.

( Platform Designer systems only) • Click Sync All System Info to validate a system's generic components against companion files. ( Platform Designer systems only) The IP Catalog is also available in Platform Designer ( View >IP Catalog). The Platform Designer IP Catalog includes exclusive system interconnect, video and image processing, and other system-level IP that are not available in the Intel ® Quartus ® Prime IP Catalog. Refer to Creating a System with Platform Designer or Creating a System with Platform Designer for information on use of IP in Platform Designer and Platform Designer, respectively. The Intel ® Quartus ® Prime software installation includes the Intel ® FPGA IP library.

This library provides many useful IP cores for your production use without the need for an additional license. Some Intel ® FPGA IP cores require purchase of a separate license for production use. The Intel ® FPGA IP Evaluation Mode allows you to evaluate these licensed Intel ® FPGA IP cores in simulation and hardware, before deciding to purchase a full production IP core license.

You only need to purchase a full production license for licensed Intel ® IP cores after you complete hardware testing and are ready to use the IP in production. The Intel ® Quartus ® Prime software installs IP cores in the following locations by default. Follow these steps to locate, instantiate, and customize an IP core in the parameter editor: • Create or open an Intel ® Quartus ® Prime project (.qpf) to contain the instantiated IP variation. • In the IP Catalog ( Tools >IP Catalog), locate and double-click the name of the IP core to customize.

To locate a specific component, type some or all of the component’s name in the IP Catalog search box. The New IP Variation window appears. • Specify a top-level name for your custom IP variation. Do not include spaces in IP variation names or paths. The parameter editor saves the IP variation settings in a file named.ip. The parameter editor appears.

• Set the parameter values in the parameter editor and view the block diagram for the component. The Parameterization Messages tab at the bottom displays any errors in IP parameters. Note: Refer to your IP core user guide for information about specific IP core parameters.

• Click Generate HDL. The Generation dialog box appears. • Specify output file generation options, and then click Generate.

The synthesis and simulation files generate according to your specifications. • To generate a simulation testbench, click Generate >Generate Testbench System. Specify testbench generation options, and then click Generate. • To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate >Show Instantiation Template. • Click Finish. Click Yes if prompted to add files representing the IP variation to your project. • After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.

Note: Some IP cores generate different HDL implementations according to the IP core parameters. The underlying RTL of these IP cores contains a unique hash code that prevents module name collisions between different variations of the IP core. This unique code remains consistent, given the same IP settings and software version during IP generation.

This unique code can change if you edit the IP core's parameters or upgrade the IP core version. To avoid dependency on these unique codes in your simulation environment, refer to Generating a Combined Simulator Setup Script. Output Files of Intel ® FPGA IP Generation File Name Description.ip Top-level IP variation file that contains the parameterization of an IP core in your project. If the IP variation is part of a Platform Designer system, the parameter editor also generates a.qsys file..cmp The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you use in VHDL design files.

_generation.rpt IP or Platform Designer generation log file. Displays a summary of the messages during IP generation..qgsimc ( Platform Designer systems only) Simulation caching file that compares the.qsys and.ip files with the current parameterization of the Platform Designer system and IP core.

This comparison determines if Platform Designer can skip regeneration of the HDL..qgsynth ( Platform Designer systems only) Synthesis caching file that compares the.qsys and.ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL..qip Contains all information to integrate and compile the IP component..csv Contains information about the upgrade status of the IP component..bsf A symbol representation of the IP variation for use in Block Diagram Files (.bdf)..spd Input file that ip-make-simscript requires to generate simulation scripts. The.spd file contains a list of files you generate for simulation, along with information about memories that you initialize..ppf The Pin Planner File (.ppf) stores the port and node assignments for IP components you create for use with the Pin Planner. _bb.v Use the Verilog blackbox ( _bb.v) file as an empty module declaration for use as a blackbox. _inst.v or _inst.vhd HDL example instantiation template. Copy and paste the contents of this file into your HDL file to instantiate the IP variation..regmap If the IP contains register information, the Intel ® Quartus ® Prime software generates the.regmap file.

The.regmap file describes the register map information of master and slave interfaces. This file complements the.sopcinfo file by providing more detailed register information about the system. This file enables register display views and user customizable statistics in System Console..svd Allows HPS System Debug tools to view the register maps of peripherals that connect to HPS within a Platform Designer system. During synthesis, the Intel ® Quartus ® Prime software stores the.svd files for slave interface visible to the System Console masters in the.sof file in the debug session. System Console reads this section, which Platform Designer queries for register map information. For system slaves, Platform Designer accesses the registers by name..v.vhd HDL files that instantiate each submodule or child IP core for synthesis or simulation. Mentor/ Contains a msim_setup.tcl script to set up and run a ModelSim simulation.

Aldec/ Contains a Riviera*-PRO script rivierapro_setup.tcl to setup and run a simulation. /synopsys/vcs /synopsys/vcsmx Contains a shell script vcs_setup.sh to set up and run a VCS* simulation. Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to set up and run a VCS MX* simulation. /cadence Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation. /submodules Contains HDL files for the IP core submodule. / Platform Designer generates /synth and /sim sub-directories for each IP submodule directory that Platform Designer generates. Modifying an IP Variation.

Modifying an IP Variation Menu Command Action File >Open Select the top-level HDL (.v, or.vhd) IP variation file to launch the parameter editor and modify the IP variation. Regenerate the IP variation to implement your changes. View >Project Navigator >IP Components Double-click the IP variation to launch the parameter editor and modify the IP variation. Regenerate the IP variation to implement your changes. Project >Upgrade IP Components Select the IP variation and click Upgrade in Editor to launch the parameter editor and modify the IP variation. Regenerate the IP variation to implement your changes.

Upgrading IP Cores. Note: Upgrading IP cores may append a unique identifier to the original IP core entity names, without similarly modifying the IP instance name. There is no requirement to update these entity references in any supporting Intel ® Quartus ® Prime file, such as the Intel ® Quartus ® Prime Settings File (.qsf), Synopsys ® Design Constraints File (.sdc), or Signal Tap File (.stp), if these files contain instance names. The Intel ® Quartus ® Prime software reads only the instance name and ignores the entity name in paths that specify both names. Use only instance names in assignments. Indicates that the current version of the Intel ® Quartus ® Prime software does not support compilation of your IP variation.

This can occur if another edition of the Intel ® Quartus ® Prime software, such as the Intel ® Quartus ® Prime Standard Edition, generated this IP. Replace this IP component with a compatible component in the current edition. Follow these steps to upgrade IP cores: • In the latest version of the Intel ® Quartus ® Prime software, open the Intel ® Quartus ® Prime project containing an outdated IP core variation.

The Upgrade IP Components dialog box automatically displays the status of IP cores in your project, along with instructions for upgrading each core. To access this dialog box manually, click Project >Upgrade IP Components. • To upgrade one or more IP cores that support automatic upgrade, ensure that you turn on the Auto Upgrade option for the IP cores, and click Auto Upgrade. The Status and Version columns update when upgrade is complete. Example designs that any Intel ® FPGA IP core provides regenerate automatically whenever you upgrade an IP core. • To manually upgrade an individual IP core, select the IP core and click Upgrade in Editor (or simply double-click the IP core name).

The parameter editor opens, allowing you to adjust parameters and regenerate the latest version of the IP core. • To upgrade a single IP core at the command-line, type the following command: quartus_sh –ip_upgrade –variation_files.

Example:quartus_sh -ip_upgrade -variation_files mega/pll25.qsys hps_testx • To simultaneously upgrade multiple IP cores at the command-line, type the following command: quartus_sh –ip_upgrade –variation_files “. ” Example:quartus_sh -ip_upgrade -variation_files ' mega/pll_tx2.qsys;mega/pll3.qsys' hps_testx Migrating IP Cores to a Different Device. Migrate an Intel ® FPGA IP variation when you want to target a different (often newer) device. Most Intel ® FPGA IP cores support automatic migration. Some IP cores require manual IP regeneration for migration.

A few IP cores do not support device migration, requiring you to replace them in the project. The Upgrade IP Components dialog box identifies the migration support level for each IP core in the design. • To display the IP cores that require migration, click Project >Upgrade IP Components. The Description field provides migration instructions and version differences.

• To migrate one or more IP cores that support automatic upgrade, ensure that the Auto Upgrade option is turned on for the IP cores, and click Perform Automatic Upgrade. The Status and Version columns update when upgrade is complete. • To migrate an IP core that does not support automatic upgrade, double-click the IP core name, and click OK. The parameter editor appears. If the parameter editor specifies a Currently selected device family, turn off Match project/default, and then select the new target device family. • Click Generate HDL, and confirm the Synthesis and Simulation file options.

Verilog HDL is the default output file format. If you specify VHDL as the output format, select VHDL to retain the original output format. • Click Finish to complete migration of the IP core. Click OK if the software prompts you to overwrite IP core files.

The Device Family column displays the new target device name when migration is complete. • To ensure correctness, review the latest parameters in the parameter editor or generated HDL. Note: IP migration may change ports, parameters, or functionality of the IP variation. These changes may require you to modify your design or to re-parameterize your IP variant. During migration, the IP variation's HDL generates into a library that is different from the original output location of the IP core.

Update any assignments that reference outdated locations. If a symbol in a supporting Block Design File schematic represents your upgraded IP core, replace the symbol with the newly generated.bsf. Migration of some IP cores requires installed support for the original and migration device families. IP Upgrade Error Information Upgrade IP Components Field Description Status Displays the 'Success' or 'Failed' status of each upgrade or migration.

Click the status of any upgrade that fails to open the IP Upgrade Report. Version Dynamically updates the version number when upgrade is successful. The text is red when the IP requires upgrade. Device Family Dynamically updates to the new device family when migration is successful. The text is red when the IP core requires upgrade. Auto Upgrade Runs automatic upgrade on all IP cores that support auto upgrade. Also, automatically generates a / ip_upgrade_port_diff_report report for IP cores or Platform Designer systems that fail upgrade.

Review these reports to determine any port differences between the current and previous IP core version. Use the following techniques to resolve errors if your IP core or Platform Designer system 'Failed' to upgrade versions or migrate to another device. Review and implement the instructions in the Description field, including one or more of the following: • If the current version of the software does not support the IP variant, right-click the component and click Remove IP Component from Project. Replace this IP core or Platform Designer system with the one supported in the current version of the software. • If the current target device does not support the IP variant, select a supported device family for the project, or replace the IP variant with a suitable replacement that supports your target device. • If an upgrade or migration fails, click Failed in the Status field to display and review details of the IP Upgrade Report.

Click the Release Notes link for the latest known issues about the IP core. Use this information to determine the nature of the upgrade or migration failure and make corrections before upgrade. • Run Auto Upgrade to automatically generate an IP Ports Diff report for each IP core or Platform Designer system that fails upgrade. Review the reports to determine any port differences between the current and previous IP core version. Click Upgrade in Editor to make specific port changes and regenerate your IP core or Platform Designer system. • If your IP core or Platform Designer system does not support Auto Upgrade, click Upgrade in Editor to resolve errors and regenerate the component in the parameter editor. The Intel ® Quartus ® Prime software supports IP core RTL simulation in specific EDA simulators.

IP generation creates simulation files, including the functional simulation model, any testbench (or example design), and vendor-specific simulator setup scripts for each IP core. Use the functional simulation model and any testbench or example design for simulation. IP generation output may also include scripts to compile and run any testbench. The scripts list all models or libraries you require to simulate your IP core. The Intel ® Quartus ® Prime software provides integration with many simulators and supports multiple simulation flows, including your own scripted and custom simulation flows.

Whichever flow you choose, IP core simulation involves the following steps: • Generate simulation model, testbench (or example design), and simulator setup script files. • Set up your simulator environment and any simulation scripts. • Compile simulation model libraries. • Run your simulator. Intel FPGA IP Simulation Files File Type Description File Name Simulator setup scripts Vendor-specific scripts to compile, elaborate, and simulate Intel ® FPGA IP models and simulation model library files. Optionally, generate a simulator setup script for each vendor that combines the individual IP core scripts into one file.

Source the combined script from your top-level simulation script to eliminate script maintenance. /aldec/rivierapro_setup.tcl /cadence/ncsim_setup.sh /mentor/msim_setup.tcl /synopsys/vcs/vcs_setup.sh.

Note: Intel ® FPGA IP cores support a variety of cycle-accurate simulation models, including simulation-specific IP functional simulation models and encrypted RTL models, and plain text RTL models. The models support fast functional simulation of your IP core instance using industry-standard VHDL or Verilog HDL simulators.

For some IP cores, generation only produces the plain text RTL model, and you can simulate that model. Use the simulation models only for simulation and not for synthesis or any other purposes.

Using these models for synthesis creates a nonfunctional design. Scripting IP Simulation.

Optionally, use another supported EDA tool to synthesize a design that includes Intel ® FPGA IP cores. When you generate the IP core synthesis files for use with third-party EDA synthesis tools, you can create an area and timing estimation netlist. To enable generation, turn on Create timing and resource estimates for third-party EDA synthesis tools when customizing your IP variation. The area and timing estimation netlist describes the IP core connectivity and architecture, but does not include details about the true functionality. This information enables certain third-party synthesis tools to better report area and timing estimates. In addition, synthesis tools can use the timing information to achieve timing-driven optimizations and improve the quality of results. The Intel ® Quartus ® Prime software generates the _syn.v netlist file in Verilog HDL format, regardless of the output file format you specify.

If you use this netlist for synthesis, you must include the IP core wrapper file.v or.vhd in your Intel ® Quartus ® Prime project. Instantiating IP Cores in HDL. Library ieee;use ieee.std_logic_1164.all; library altera_mf;use altera_mf.altera_mf_components.all; entity MF_top is port (clock, sel: in std_logic; a, b, datab: in std_logic_vector(31 downto 0); result: out std_logic_vector(31 downto 0));end entity;architecture arch_MF_top of MF_top issignal wire_dataa: std_logic_vector(31 downto 0);beginwire_dataa 11, width_exp =>8, width_man =>23, exception_handling =>'no') port map ( dataa =>wire_dataa, datab =>datab, clock =>clock, result =>result);end arch_MF_top; Support for the IEEE 1735 Encryption Standard. Optionally integrate supported EDA design entry, synthesis, simulation, physical synthesis, and formal verification tools into the Intel ® Quartus ® Prime design flow. The Intel ® Quartus ® Prime software supports netlist files from other EDA design entry and synthesis tools. The Intel ® Quartus ® Prime software optionally generates various files for use in other EDA tools. The Intel ® Quartus ® Prime software manages EDA tool files and provides the following integration capabilities: • Compile all RTL and gate-level simulation model libraries for your device, simulator, and design language automatically ( Tools >Launch Simulation Library Compiler).

• Include files generated by other EDA design entry or synthesis tools in your project as synthesized design files ( Project >Add/Remove File from Project). • Automatically generate optional files for board-level verification ( Assignments >Settings >EDA Tool Settings). Managing Team-based Projects. The Intel ® Quartus ® Prime software allows you to transfer your compiled databases from one version of the software to a newer version of the software. You can export the results of compilation at various stages of the compilation flow, such as synthesis, planned, early place, place, route, and finalize snapshots.

A snapshot is the compilation output of a compiler stage. Import allows you to restore the preserved compilation database and run subsequent stages in the compiler flow.

Export the compilation snapshot by clicking Project >Export Design. The exported files are stored in a file with a.qdb extension. Import the snapshot with Project >Import Design. • Project Files—project settings (.qsf, quartus2.ini), design files, and timing constraints (.sdc). Any setting that changes the number of processors during compilation can impact compilation results. • Hardware—CPU architecture, not including hard disk or memory size differences.

Windows XP x32 results are not identical to Windows XP x64 results. Linux x86 results is not identical to Linux x86_64. • Intel ® Quartus ® Prime Software Version—including build number and installed interim updates. Click Help >About to obtain this information. • Operating System—Windows or Linux operating system, excluding version updates. For example, Windows XP, Windows Vista, and Windows 7 results are identical. Similarly, Linux RHEL, CentOS 4, and CentOS 5 results are identical.

• Open the project for exporting the compilation results in the Intel ® Quartus ® Prime software. • Generate the project database and netlist with one of the following: • Click Processing >Start >Start Analysis & Synthesis to generate a post-synthesis netlist. • Click Processing >Start Compilation to generate a post-fit netlist. • Click Project >Export Design.

Select the Snapshot for export. A Intel ® Quartus ® Prime Core Database Archive File (.qdb) preserves the database. You can select one of the following Snapshots: • synthesized—represents the output of analysis & synthesis. • final—represents the output of the Fitter. • In a newer version of the Intel ® Quartus ® Prime software, click New Project Wizard and create a new project with the same top-level design entity name as the database. • Click Project >Import Design and specify the Intel ® Quartus ® Prime Core Database Archive File that contains the exported results.

The Timing analysis mode option disables legality checks for certain configuration rules that may have changed from prior versions of the Intel ® Quartus ® Prime software. Use this option only if you cannot successfully import your design without it. After you have imported a design in timing analysis mode, you cannot use it to generate programming files. The Overwrite existing project's databases option removes all prior compilation databases from the current project before importing the specified Core Database Archive File. Optionally save the elements of a project in a single, compressed Intel ® Quartus ® Prime Archive File (.qar) by clicking Project >Archive Project. The.qar preserves logic design, project, and settings files required to restore the project.

Use this technique to share projects between designers, or to transfer your project to a new version of the Intel ® Quartus ® Prime software, or to Intel support. Optionally add compilation results, Platform Designer system files, and third-party EDA tool files to the archive. If you restore the archive in a different version of the Intel ® Quartus ® Prime software, you must include the original.qdf in the archive to preserve original compilation results. Your project may involve different team members with distributed responsibilities, such as sub-module design, device and system integration, simulation, and timing closure.

In such cases, it may be useful to track and protect file revisions in an external revision control system. While Intel ® Quartus ® Prime project revisions preserve various project setting and constraint combinations, external revision control systems can also track and merge RTL source code, simulation testbenches, and build scripts.

External revision control supports design file version experimentation through branching and merging different versions of source code from multiple designers. Refer to your external revision control documentation for setup information. • Logic design files (.v,. Vdh,.bdf,.edf,.vqm) • Timing constraint files (.sdc) • Quartus project settings and constraints (.qdf,.qpf,.qsf) • IP files (.ip,.v,.sv,.vhd,.qip,.sip,.qsys) • Platform Designer-generated files (.qsys,.ip,.sip) • EDA tool files (.vo,.vho ) Generate or modify these files manually if you use a scripted design flow. If you use an external source code control system, check-in project files anytime you modify assignments and settings. Migrating Projects Across Operating Systems. • Use appropriate case for your platform in file path references.

• Use a character set common to both platforms. • Do not change the forward‑slash ( /) and back‑slash ( ) path separators in the.qsf. The Intel ® Quartus ® Prime software automatically changes all back‑slash ( ) path separators to forward‑slashes ( / )in the.qsf. • Observe the target platform’s file name length limit.

• Use underscore instead of spaces in file and directory names. • Change library absolute path references to relative paths in the.qsf.

• Ensure that any external project library exists in the new platform’s file system. • Specify file and directory paths as relative to the project directory.

For example, for a project titled foo_design, specify the source files as: top.v, foo_folder /foo1.v, foo_folder /foo2.v, and foo_folder/bar_folder/bar1.vhdl. • Ensure that all the subdirectories are in the same hierarchical structure and relative path as in the original platform. • The project directory takes precedence over the project libraries. • For Linux, the Intel ® Quartus ® Prime software creates the file in the altera.quartus directory under the directory.

• All library files are relative to the libraries. For example, if you specify the user_lib1 directory as a project library and you want to add the /user_lib1/foo1.v file to the library, you can specify the foo1.v file in the.qsf as foo1.v. The Intel ® Quartus ® Prime software includes files in specified libraries. • If the directory is outside of the project directory, an absolute path is created by default.

Change the absolute path to a relative path before migration. • When copying projects that include libraries, you must either copy your project library files along with the project directory or ensure that your project library files exist in the target platform. • On Windows, the Intel ® Quartus ® Prime software searches for the quartus2.ini file in the following directories and order: • USERPROFILE, for example, C: Documents and Settings • Directory specified by the TMP environmental variable • Directory specified by the TEMP environmental variable • Root directory, for example, C: Scripting API. Project_archive.qar You can specify the following other options: • -all_revisions - Includes all revisions of the current project in the archive. • -auto_common_directory - Preserves original project directory structure in archive • -common_directory / - Preserves original project directory structure in specified subdirectory • -include_libraries - Includes libraries in archive • -include_outputs - Includes output files in archive • -use_file_set - Includes specified fileset in archive Restoring an Archived Project. Optionally use Tcl commands to export and import a full design.

You must not open the project or load the database before calling these commands. These commands require the quartus_cdb executable. • To export a design’s snapshot to a file: design::export_design -file -snapshot • To import an exported design’s snapshot into a project: design::import_design -file [-overwrite] [-timing_analysis_mode] The -overwrite option removes existing project compilation databases before importing the archived.qdb file. The -timing_analysis_mode option is only available for Intel ® Arria ® 10 designs. The option disables legality checks for certain configuration rules that may have changed from prior versions of the Intel ® Quartus ® Prime software.

Use this option only if you cannot successfully import your design without the option. After you import a design in timing analysis mode, you cannot use the imported design to generate programming files. Quartus_cdb Executables to Manage Version-Compatible Databases. The command-line arguments to the quartus_cdb executable in the Quartus Prime Pro software are export_design and import_design. The exported version-compatible design files are archived in a file (with a.qdb extension). This differs from the Intel ® Quartus ® Prime Standard Edition software, which writes all files to a directory.

In the Intel ® Quartus ® Prime Standard Edition software, the flow exports both post-map and post-fit databases. In the Intel ® Quartus ® Prime Pro Edition software, the export command requires the snapshot argument to indicate the target snapshot to export. If the specified snapshot has not been compiled, the flow exits with an error. In ACDS 16.0, export is limited to “synthesized” and “final” snapshots. Quartus_cdb [-c ] --export_design --snapshot --file.qdb The import command takes the exported *.qdb file and the project to which you want to import the design. Quartus_cdb [-c ] --import_design --file.qdb [--overwrite] [--timing_analysis_mode] The --timing_analysis_mode option is only available for Intel ® Arria ® 10 designs. The option disables legality checks for certain configuration rules that may have changed from prior versions of the Intel ® Quartus ® Prime software.

Use this option only if you cannot successfully import your design without it. After you have imported a design in timing analysis mode, you cannot use it to generate programming files. Project Library Commands. Document Revision History Date Version Changes 2017.11.06 17.1.0 • Revised product branding for Intel ® standards. • Revised topics on Intel ® FPGA IP Evaluation Mode (formerly OpenCore). • Removed -compatible attribute from export_design command content.

• Updated figure: IP Upgrade Alert in Project Navigator. • Updated IP Core Upgrade Status table with new icons, and added row for IP Component Outdated status.

2017.05.08 17.0.0 • Added Project Tasks pane and update New Project Wizard. • Updated Compilation Dashboard image to show concurrent analysis. • Removed Smart Compilation option from Settings dialog box screenshot. • Updated IP Catalog screenshots for latest GUIs. • Added topic on Back-Annotate Assignments command. • Added Exporting a Design Partition topic.

• Removed mentions to deprecated Incremental Compilation. • Added reference to Block-Level Design Flows. 2016.10.31 16.1.0 • Added references to compilation stages and snapshots. • Removed support for comparing revisions. • Added references to.ip file creation during Intel ® Quartus ® Prime Pro Edition stand-alone IP generation. • Updated IP Core Generation Output files list and diagram. • Added Support for IP Core Encyption topic.

• Rebranding for Intel 2016.05.03 16.0.0 • Removed statements about serial equivalence when using multiple processors. • Added the 'Preserving Compilation Results' section. • Added the 'Migrating Results Across Quartus Prime Software' section and its subsections for information about importing and exporting compilation results between different versions of Quartus Prime. • Added the 'Project Database Commands' section and its subsections. 2016.02.09 15.1.1 • Clarified instructions for Generating a Combined Simulator Setup Script. • Clarified location of Save project output files in specified directory option.

2015.11.02 15.1.0 • Added Generating Version-Independent IP Simulation Scripts topic. • Added example IP simulation script templates for supported simulators. • Added Incorporating IP Simulation Scripts in Top-Level Scripts topic. • Added Troubleshooting IP Upgrade topic. • Updated IP Catalog and parameter editor descriptions for GUI changes.

• Updated IP upgrade and migration steps for latest GUI changes. • Updated Generating IP Cores process for GUI changes. • Updated Files Generated for IP Cores and Qsys system description.

• Removed references to devices and features not supported in version 15.1. • Changed instances of Quartus II to Intel ® Quartus ® Prime. 2015.05.04 15.0.0 • Added description of design templates feature.

• Updated screenshot for DSE II GUI. • Added qsys_script IP core instantiation information. • Described changes to generating and processing of instance and entity names. • Added description of upgrading IP cores at the command line. • Updated procedures for upgrading and migrating IP cores.

• Gate level timing simulation supported only for Cyclone IV and Stratix IV devices. 2014.12.15 14.1.0 • Updated content for DSE II GUI and optimizations. • Added information about new Assignments >Settings >IP Settings that control frequency of synthesis file regeneration and automatic addtion of IP files to the project.

2014.08.18 14.0a10.0 • Added information about specifying parameters for IP cores targeting Arria 10 devices. • Added information about the latest IP output for version 14.0a10 targeting Arria 10 devices.

• Added information about individual migration of IP cores to the latest devices. • Added information about editing existing IP variations. 2014.06.30 14.0.0 • Replaced MegaWizard Plug-In Manager information with IP Catalog. • Added standard information about upgrading IP cores. • Added standard installation and licensing information.

• Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor. November 2013 13.1.0 • Conversion to DITA format May 2013 13.0.0 • Overhaul for improved usability and updated information. June 2012 12.0.0 • Removed survey link. • Updated information about VERILOG_INCLUDE_FILE. November 2011 10.1.1 Template update.

December 2010 10.1.0 • Changed to new document template. • Removed Figure 4–1, Figure 4–6, Table 4–2. • Moved “Hiding Messages” to Help. • Removed references about the set_user_option command. • Removed Classic Timing Analyzer references. Note: The Interface Planner helps you to accurately plan constraints for design implementation. Use Interface Planner to prototype interface implementations and rapidly define a legal device floorplan for Intel ® Arria ® 10 devices.

Before reading the design planning guidelines discussed in this chapter, consider your design priorities. More device features, density, or performance requirements can increase system cost. Signal integrity and board issues can impact I/O pin locations. Power, timing performance, and area utilization all affect each other. Compilation time is affected when optimizing these priorities. The Intel ® Quartus ® Prime software optimizes designs for the best overall results; however, you can change the settings to better optimize one aspect of your design, such as power utilization.

Certain tools or debugging options can lead to restrictions in your design flow. Your design priorities help you choose the tools, features, and methodologies to use for your design.

After you select a device family, to check if additional guidelines are available, refer to the design guidelines section of the appropriate device documentation. Before you create your design logic or complete your system design, create detailed design specifications that define the system, specify the I/O interfaces for the FPGA, identify the different clock domains, and include a block diagram of basic design functions. In addition, creating a test plan helps you to design for verification and ease of manufacture.

For example, you might need to validate interfaces incorporated in your design. To perform any built-in self-test functions to drive interfaces, you can use a UART interface with a Nios ® II processor inside the FPGA device.

If more than one designer works on your design, you must consider a common design directory structure or source control system to make design integration easier. Consider whether you want to standardize on an interface protocol for each design block.

Because system design tools change the design entry methodology, you must plan to start developing your design within the tool. Ensure all design blocks use appropriate standard interfaces from the beginning of the design cycle so that you do not need to make changes later. Platform Designer components use Avalon ® standard interfaces for the physical connection of components, and you can connect any logical device (either on-chip or off-chip) that has an Avalon interface.

The Avalon Memory-Mapped interface allows a component to use an address mapped read or write protocol that enables flexible topologies for connecting master components to any slave components. The Avalon Streaming interface enables point-to-point connections between streaming components that send and receive data using a high-speed, unidirectional system interconnect between source and sink ports. In addition to enabling the use of a system integration tool such as Platform Designer, using standard interfaces ensures compatibility between design blocks from different design teams or vendors. Standard interfaces simplify the interface logic to each design block and enable individual team members to test their individual design blocks against the specification for the interface protocol to ease system integration. Choose the device family that best suits your design requirements.

Families differ in cost, performance, logic and memory density, I/O density, power utilization, and packaging. You must also consider feature requirements, such as I/O standards support, high-speed transceivers, global or regional clock networks, and the number of phase-locked loops (PLLs) available in the device.

Each device family has complete documentation, including a data sheet, which documents device features in detail. You can also see a summary of the resources for each device in the Device dialog box in the Intel ® Quartus ® Prime software.

Carefully study the device density requirements for your design. Devices with more logic resources and higher I/O counts can implement larger and more complex designs, but at a higher cost. Smaller devices use lower static power. Select a device larger than what your design requires if you want to add more logic later in the design cycle to upgrade or expand your design, and reserve logic and memory for on-chip debugging. Consider requirements for types of dedicated logic blocks, such as memory blocks of different sizes, or digital signal processing (DSP) blocks to implement certain arithmetic functions.

If you have older designs that target an Intel device, you can use their resources as an estimate for your design. Compile existing designs in the Intel ® Quartus ® Prime software with the Auto device selected by the Fitter option in the Settings dialog box. Review the resource utilization to learn which device density fits your design. Consider coding style, device architecture, and the optimization options used in the Intel ® Quartus ® Prime software, which can significantly affect the resource utilization and timing performance of your design.

Determine whether you want to migrate your design to another device density to allow flexibility when your design nears completion. You may want to target a smaller (and less expensive) device and then move to a larger device if necessary to meet your design requirements. Other designers may prototype their design in a larger device to reduce optimization time and achieve timing closure more quickly, and then migrate to a smaller device after prototyping. If you want the flexibility to migrate your design, you must specify these migration options in the Intel ® Quartus ® Prime software at the beginning of your design cycle. Follow the steps below to select a development kit for a new Intel ® Quartus ® Prime project: • To open the New Project Wizard, click File >New Project Wizard.

• Click the Board tab from Family, Device & Board Settings page. • Select the Family and Development Kit lists to narrow your board search. The Available boards table lists all the available boards for the selected Family and Development Kit type. • To view the development kit details for each of the listed boards, click the icons to the left of the boards in the Available boards table. The Development Kit Details dialog box appears, displaying all the board details. • Select the desired board from the Available boards table.

• To set the selected board design as top-level entity, click the Create top-level design file checkbox. This option automatically sets up the pin assignments for the selected board. If you choose to uncheck this option, the Intel ® Quartus ® Prime software creates the design for the board and stores the design in /devkits/. • Click Finish. Follow the steps below to select a development kit for your existing Intel ® Quartus ® Prime project: • To open your existing project, click File >Open Project. • To open the Device Setting Dialog Box, click Assignments >Device. • Select the desired development kit from the Board tab and click OK.

• If there are existing pin assignments in your current project, a message box appears, prompting to remove all location assignments. Click Yes to remove the Location and I/O Standard pin assignments. The Intel ® Quartus ® Prime software creates the kit's baseline design and stores the design in /devkits/.

To retain all your existing pin assignments, click No. System planning includes determining what companion devices, if any, your system requires. Your board layout also depends on the type of programming or configuration method you plan to use for programmable devices. Many programming options require a JTAG interface to connect to the devices, so you might have to set up a JTAG chain on the board.

Additionally, the Intel ® Quartus ® Prime software uses the settings for the configuration scheme, configuration device, and configuration device voltage to enable the appropriate dual purpose pins as regular I/O pins after you complete configuration. The Intel ® Quartus ® Prime software performs voltage compatibility checks of those pins during compilation of your design. Use the Configuration tab of the Device and Pin Options dialog box to select your configuration scheme.

You must accurately estimate device power consumption to develop an appropriate power budget and to design the power supplies, voltage regulators, heat sink, and cooling system. Power estimation and analysis helps you satisfy two important planning requirements: • Thermal—ensure that the cooling solution is sufficient to dissipate the heat generated by the device. The computed junction temperature must fall within normal device specifications. • Power supply—ensure that the power supplies provide adequate current to support device operation. The Early Power Estimator (EPE) spreadsheet allows you to estimate power utilization for your design.

You can manually enter data into the EPE spreadsheet, or use the Intel ® Quartus ® Prime software to generate device resource information for your design. To manually enter data into the EPE spreadsheet, enter the device resources, operating frequency, toggle rates, and other parameters for your design. If you do not have an existing design, estimate the number of device resources used in your design, and then enter the data into the EPE spreadsheet manually. If you have an existing design or a partially completed design, you can use the Intel ® Quartus ® Prime software to generate the Early Power Estimator File (.txt,.csv) to assist you in completing the EPE spreadsheet.

The EPE spreadsheet includes the Import Data macro that parses the information in the EPE File and transfers the information into the spreadsheet. If you do not want to use the macro, you can manually transfer the data into the EPE spreadsheet. For example, after importing the EPE File information into the EPE spreadsheet, you can add device resource information.

If the existing Intel ® Quartus ® Prime project represents only a portion of your full design, manually enter the additional device resources you use in the final design. Estimating power consumption early in the design cycle allows planning of power budgets and avoids unexpected results when designing the PCB. When you complete your design, perform a complete power analysis to check the power consumption more accurately.

The Power Analyzer tool in the Intel ® Quartus ® Prime software provides an accurate estimation of power, ensuring that thermal and supply limitations are met. Different synthesis tools may give different results for each design. To determine the best tool for your application, you can experiment by synthesizing typical designs for your application and coding style. Perform placement and routing in the Intel ® Quartus ® Prime software to get accurate timing analysis and logic utilization results. The synthesis tool you choose may allow you to create a Intel ® Quartus ® Prime project and pass constraints, such as the EDA tool setting, device selection, and timing requirements that you specified in your synthesis project. You can save time when setting up your Intel ® Quartus ® Prime project for placement and routing. Tool vendors frequently add new features, fix tool issues, and enhance performance for Intel devices, you must use the most recent version of third-party synthesis tools.

Simulation Tool. Using a formal verification tool can impact performance results because performing formal verification requires turning off certain logic optimizations, such as register retiming, and forces you to preserve hierarchy blocks, which can restrict optimization. Formal verification treats memory blocks as black boxes. Therefore, you must keep memory in a separate hierarchy block so other logic does not get incorporated into the black box for verification. If formal verification is important to your design, plan for limitations and restrictions at the beginning of the design cycle rather than make changes later. Planning for On-Chip Debugging Tools. In-system debugging tools offer different advantages and trade-offs.

A particular debugging tool may work better for different systems and designers. Consider the following debugging requirements when you plan your design: • JTAG connections—required to perform in-system debugging with JTAG tools. Plan your system and board with JTAG ports that are available for debugging.

• Additional logic resources (ALR)—required to implement JTAG hub logic. If you set up the appropriate tool early in your design cycle, you can include these device resources in your early resource estimations to ensure that you do not overload the device with logic. • Reserve device memory—required if your tool uses device memory to capture data during system operation. To ensure that you have enough memory resources to take advantage of this debugging technique, consider reserving device memory to use during debugging. • Reserve I/O pins—required if you use the Logic Analyzer Interface (LAI), which require I/O pins for debugging. If you reserve I/O pins for debugging, you do not have to later change your design or board. The LAI can multiplex signals with design I/O pins if required.

Ensure that your board supports a debugging mode, in which debugging signals do not affect system operation. • Instantiate an IP core in your HDL code—required if your debugging tool uses an Intel FPGA IP core. • Instantiate the Signal Tap Logic Analyzer IP core—required if you want to manually connect the Signal Tap Logic Analyzer to nodes in your design and ensure that the tapped node names do not change during synthesis.